The present invention generally relates to semiconductor devices having a silicon on insulator structure, and more particularly to a semiconductor device having a silicon on insulator structure with a stable electrical characteristic.
A known semiconductor device having a silicon on insulator (hereinafter simply referred to as an SOI) structure is produced by forming a relatively thick insulator layer on a semiconductor substrate, forming a polysilicon layer on the insulator layer by a chemical vapor deposition, forming the polysilicon layer into a single crystal silicon layer by irradiating an energy beam or the like, forming an insular single crystal silicon body by a patterning process, and forming a semiconductor device on the insular single crystal silicon body. According to the SOI structure, a semiconductor integrated circuit (IC) including high voltage elements can be formed with ease because the isolation between elements is positively provided. In addition, the integration density of the semiconductor IC can be improved by employing a three-dimensional structure.
However, according to a conventional metal insulator semiconductor (hereinafter simply referred to as MIS) device having the SOI structure, it is impossible to apply a fixed voltage to the insular body on which the elements are formed. As a result, the insular body is in a floating state, and a leakage current is easily generated between a source and a drain due to a back channel at a lower portion of the insular body. Thus, there is a problem in that the electrical characteristic of the MIS device is unstable. Hence, there is a demand to realize a MIS device having the SOI structure in which it is possible to apply the fixed voltage to the insular body.
As a method of preventing the back channel without providing a contact for the insular body, there is a method of setting the impurity density of the insular body to a high density, but this method is impractical in that a current gain becomes greatly reduced.
On the other hand, the crystal property of the insular single crystal silicon body formed on the insulator layer of the SOI structure is deteriorated compared to that of a silicon substrate which is generally used. For this reason, the diffusion rate of impurities is extremely fast for the insular single crystal silicon body compared to that of the silicon substrate, and it is difficult to limit the depth of the impurity diffusion region under the thickness of the insular single crystal silicon body.
Metal oxide semiconductor (MOS) devices in which it is possible to apply a fixed voltage to the insular body are previously proposed in Japanese Laid-Open Patent Applications No. 57-27069 and No. 58-37966. According to these previously proposed devices, an insular p-type silicon body is formed on an insulating substrate made of sapphire, for example. An n.sup.+ -type source region and a p-type channel region adjacent thereto are provided in the insular body down to a boundary between the insulating substrate and the insular body. An n.sup.+ -type drain region is provided in the surface portion of the channel region, at a position separated from the source region. A p.sup.+ -type impurity region is provided adjacent to the channel region and the drain region down to the boundary. A gate electrode is provided on the channel region via a gate insulator layer. Hence, a fixed voltage may be applied to the channel region via the p.sup.+ -type impurity region which connects to a lower portion of the channel region under the drain region.
However, the thickness of the insular body is in the order of one micron, and the thickness of the drain region provided in the surface portion of the channel region is in the order of 0.2 micron. In actual practice, it is extremely difficult to control the thickness of the drain region to such a small thickness so that the drain region does not reach the boundary between the insulating substrate and the insular body when the insular body is made of single crystal silicon, as described before. Hence, there is a problem in that it is extremely difficult to produce such MOS devices.
In addition, according to the previously proposed devices, there is a problem in that the electrical characteristic of the MOS device changes depending on a positioning error of the gate electrode when the device is produced. Furthermore, there is a problem in that the width of the gate electrode cannot be set to a small value because the p.sup.+ -type impurity region will make contact with junctions between the channel region and the source and drain regions and cause a short circuit when the width of the gate electrode is narrow.